Design-for-Testability (DFT) Engineer, Autopilot AI (Austin)

Tesla

  • Full Time

Role 

Tesla’s Silicon Development Group is looking for a DFx (Design for Test/debug & manufacturability) Engineer to work on custom and semi-custom ASIC design-to-production. You will also drive/push state of the art in the areas of testability, debug and safety to drive coverages, quality, and safety, in order to aggressively deliver very low DPPM’s, while optimizing the cost for test.  

Responsibilities

  • Drive the quality of the products from Design to Production
  • Participate/contribute in silicon bring-up, characterization, and silicon test
  • Define and implement various DFx features

Requirements

  • Knowledge of Testability techniques and features (SCAN, Built-in-Self-Tests, Loop-Backs etc.) covering digital logic domain, embedded memories and PHY/IO’s
  • Scan/LBIST flow development, ATPG pattern generation, verification and coverage analysis
  • Experience working with Cadence DFT tools (Modus and Genus) or Mentor DFT tools (Tessent and MBIST architect) preferred
  • Well versed in JTAG/1500/1687 networks. BSDL, ICL and PDL knowledge preferable
  • Strong knowledge of logic & circuit design fundamentals is needed
  • Knowledge of Verilog or System-Verilog
  • Working knowledge of TCL, python (or another scripting language like Perl)
  • Degree in Computer Engineering or Electrical Engineering or equivalent experience with evidence of exceptional abilities 
  • Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a plus
  • Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus
  • Experience in implementation of MBIST for memories and knowledge of repair schemes, algorithms is a plus
  • Experience or working knowledge of SERDES, Analog /mixed-signal DFT techniques (like IOBIST, loop-backs etc..) is a plus
  • Post Silicon experience in Pattern conversion for Testers, Pattern Bring-up & Debug, Silicon Characterization etc. is a plus
  • Experience or familiarity in back-end chip design, Timing, CDC flows is a plus